ADAS/AD Master Chip Research: Weaknesses and Disruption in the Integration Trend
L2 vehicles are gaining ground as penetration is over 15%. A rash of L2.5 vehicle launches is drawing near. Mass production of L3 and L4 (limited scenarios) is also around the corner.
The march toward highly automated vehicles requires installation of a large number of environmental sensors, and master chips to offer ever stronger compute and algorithms.
Single type of automotive processors, whatever FPGA/CPU/GPU or ASIC, are not competent enough to meet the needs of highly automated vehicles. SoC (master chip), a fusion of computing elements like CPU, GPU, NPU and ISP, grows a great concern of the competitive market.
In the master chip field, vendors follow different technology roadmaps, and the mainstream solution is heterogeneous fusion of chips of differing types. CPU assumes logical operation and task scheduling; GPU as a universal accelerator undertakes tasks of neural network computing (e.g., CNN) and machine learning, and will work on computing for quite a long time; FPGA as hardware accelerator that is programmable and performs well in sequential machine learning (e.g., RNN/LSTM/reinforcement learning), plays a prominent role in some mature algorithms; ASIC, as fully customized solution with optimal performance and the least power consumption, will become the final option after automated driving algorithms get mature.
Mobileye started with conventional algorithms. EyeQ5 packs 4 modules: CPU, CVP (Computer Vision Processor), DLA (Deep Learning Accelerator) and MA. By size, CPU and CVP remain large. CPU has a big footprint; CVP acts as ASIC designed for a great many conventional computer vision algorithms. Mobileye is renowned for such common algorithms which are well received for low power consumption. DLA which was not written into the initial version of EyeQ5 brochure was added in just later under the market pressure as a small part of the entire chip.
Mobileye had the foresight to sell itself to Intel early for future integration with the chip giant’s CPU and FPGA technology resources. As it is not open enough and its compute still desires to be much improved, EyeQ5 captures just few automaker users, only four (publicized), far less than NVIDIA Xavior.
We suppose that Mobileye has made arduous effort into solving the problem of openness. NXP and Renesas are also stepping up efforts to overcome weaknesses not only by improving API, tool chain and ecosystem but either buying in or acquiring related companies, for example, NXP invested Kalray and Renesas purchased IDT.
As aforementioned, Mobileye’s algorithm solutions are still led by conventional computer vision algorithms and aided by deep learning algorithms, while its largest rival Nvidia focuses on deep learning algorithms.
Xavier has 4 modules: CPU, GPU, DLA (Deep Learning Accelerator) and PVA. GPU has the largest size, followed by CPU; and the two special ASICs play a subsidiary role: one is DLA for reasoning and the other is PVA for accelerating conventional computer vision algorithms.
At NVIDIA GTC 2019, NVIDIA unveiled NVIDIA DRIVE AP2X, a complete Level 2 + automated driving solution encompassing DRIVE AutoPilot software, DRIVE AGX and DRIVE validation tools. To enhance mapping and localization, DRIVE AP2X software will include MapNet, a DNN that identifies lanes and landmarks.
DRIVE AutoPilot homes in on maps and plans a safe, efficient path forward. Drive Works provides an extensive set of tools, reference applications, and documentation for developers. ClearSightNet is part of NVIDIA’s camera-based obstacle perception software, which allows the vehicle to detect camera blindness in real time and performs DNN inference on a live camera feed, evaluating each frame to detect camera blindness.
Still, NVIDIA has a drawback -- high power consumption. Chips of Qualcomm and TI only need air cooling, while those of NVIDIA and Tesla need water cooling, which is a side effect of pursuing strong computing power.
It can be seen from the table above that another heavyweight is Xilinx that has won quite a few automotive clients as well on the strength of its unique FPGA (low power consumption, low latency, and excellent cost performance). Amid ADAS/AD master chips getting integrated, Xilinx does not reconcile itself to a minor role.
In 2018, Xilinx introduced Versal ACAP, a fully software-programmable, heterogeneous compute platform that combines Scalar Engines, Adaptable Engines, and Intelligent Engines. This shows Xilinx’s ambition to transform from a specialist chip vendor into a computing platform provider.
Xilinx’s products have evolved from FPGA to SoC (FPGA that has single hard-core processors on-chip) and MPSoC (FPGA that has multiple hard-core processors on-chip), then to RFSoC (RF-enabled MPSoC) and ACAP (adaptive compute acceleration platform).
In 2019, Xilinx announced Vitis, a unified software platform that makes it easier for developers to use FPGA. Vitis software platform supports heterogeneous system architectures such as Zynq SoC, MPSoC and Versal ACAP. It automatically tailors the Xilinx hardware architecture to the software or algorithmic code for developers without the need for hardware expertise.
Xilinx introducing Vitas and Versal, in a word, aims to gear from a FPGA vendor into a flexible, adaptive computing platform provider.
In the increasingly contested ADAS/AD master chip market, besides Mobileye, NVIDIA and Xilinx that have produced good results, the time-honored automotive chip vendors like NXP and Renesas are endeavoring to jump on the bandwagon. The giants Qualcomm and Huawei from the consumer electronics field make an aggressive foray into the market; Chinese start-ups Horizon Robotics, Black Sesame Technologies and SemiDrive which are availing themselves of the wave of replacing foreign products have brought in some gains.
As integration grows a trend, no one will survive without change. Anything will be possible in an unpredictable future.
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