Synopsys and United Microelectronics (UMC) have announced an agreement to collaborate on the development of Synopsys DesignWare IP for UMC's 28nm HLP Poly SiON process.

Extending its previous successes in UMC's 40nm and 55nm processes, Synopsys plans to implement its proven DesignWare embedded memories and logic libraries in UMC's 28HLP Poly SiON process technology, the companies said. This collaboration will enable designers to create high-speed, low-power system-on-chips (SoCs) with less risk and improved time-to-market.

Synopsys revealed that its DesignWare embedded memories and logic libraries include advanced power management features such as light-sleep, deep-sleep and shut-down as well as a power optimization kit to help extend battery life in mobile applications.

Synopsys' DesignWare embedded memories and logic libraries supporting UMC's 28HLP process are scheduled to be available in the second quarter of 2012, according to the companies.

In addition, UMC noted that its 28nm Poly SiON technology is currently in pilot production and available for customer design-in now.