Automotive RISC-V Chip Industry Research Report, 2024

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Automotive RISC-V Research: Customized chips may become the future trend, and RISC-V will challenge ARM

What is RISC-V?
Reduced Instruction Set Computing - Five (RISC-V) is an open standard instruction set architecture (ISA) based on established reduced instruction set computer (RISC) principles. RISC-V can be used to design and implement processor chips and computer architectures. It competes with X86 and ARM globally.

RISC-V’s advantage mainly lies in that its instruction sets and architectures are open source and free. Its modular design allows enterprises to add, expand or remove the instruction sets. In contrast, ARM and X86 are not only complicated in instruction set development, but also difficult to obtain authorization to modify instruction sets.

However, RISC-V’s disadvantage mainly rests in the relatively immature ecosystem. Related compilers, development tools, software integrated development environment (IDE) and other ecological elements are still developing.

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RISC-V makes chip customization easier
RISC-V adopts modular ISA, that is, it consists of a basic integer instruction set (the basic integer instruction set is the only mandatory basic instruction set for RISC-V, and other instruction sets are optional extension modules) and multiple optional extension instruction sets. Therefore, a CPU can be customized according to the requirements of a specific application.

In terms of customization, it enables designers to create thousands of potential customized processors, thus speeding up the time to market. The universality of processor IP also shortens software development time.

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For example, Codasip can provide users with processor customized IP solutions based on RISC-V. The solution includes basic processor IP and development tool Codasip Studio. The engineering team can realize the integrated design of hardware and software according to project requirements and improve the efficiency of customized processor design. In October 2023, Codasip introduced the highly flexible 700 family for unlimited innovation. With the 700 family and Codasip Custom Compute, designers can push the technology limits by optimizing at the chip or application level for unique gains while keeping costs under control.

SiFive is a semiconductor enterprise based on RISC-V customization. SiFive mainly assists companies to customize processor cores based on RISC-V. Through its customized RISC-V semiconductor, it facilitates IC design and system companies to shorten the time to market and reduce costs.

RISC-V has spread to high-performance fields with the shipments of 10 billion processor cores in 2022

According to the data of RISC-V Foundation, 10 billion processor cores based on RISC-V were shipped in 2022, and are mainly used in the field of Internet of Things. With the growth of market demand, RISC-V is gradually moving towards high-performance fields such as autonomous driving, artificial intelligence, communication, data centers and other scenarios that require higher computing power.

Tesla developed its own customized chip "D1" in 2021. Based on RISC-V, D1 can train the artificial intelligence network in the data center.

Mobileye (acquired by Intel) released EyeQ Ultra in January 2022, containing 12 dual-threaded CPU cores based on RISC-V. Mass production is expected in 2025.

In September 2023, StarFive unveiled Dubhe-90, a high-performance RISC-V CPU IP. Dubhe-90 is the flagship product of Dubhe Max Performance series, with SPECint2006 9.4/GHz and performance comparable to that of ARM Cortex-A76. Its customers mainly come from high-end application fields such as PC, high-performance network communication, machine learning and data centers.

The combination of RISC-V and chiplet technology reduces the cost and threshold of chip design

In order to reduce the cost and threshold of chip design, RISC-V processor development companies and research institutions combine RISC-V with chiplet technology.

Chiplets package specific functional dies into multiple homogeneous and heterogeneous module chips through intra-chip interconnection technology (die-to-die). Chiplet technology can divide a SoC into independent modules and manufacture them separately, thus improving the yield and reducing the design cost.

In November 2023, Ventana Micro Systems Inc. announced Veyron V2, the second generation of its Veyron family of RISC-V processors. The Veyron V2 is the highest performance RISC-V processor available today and is offered in the form of chiplets and IP. The Veyron V2 chiplet features industry leading UCIe chiplet interconnect. Veyron V2’s chiplet-based solutions provide advantages in unit economics, accelerating time to market by up to two years and reducing development costs by up to 75%. Chiplet-based solutions also provide better unit economics by right sizing compute, IO, and memory.

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Nuclei System Technology, as a RISC-V CPU IP enterprise, is laying out chiplets. In November 2022, Nuclei System Technology joined the UCIe (Universal Chiplet Interconnect Express) Industry Alliance as China's first RISC-V CPU IP enterprise that did so. Nuclei System Technology will work together with other members of UCIe Industry Alliance around the world to research and apply the specifications of UCIe 1.0 and the next-generation UCIe technical standard, and will carry out hard-core IP R&D based on chiplet interconnection.

On January 9, 2024, the Institute of Computing Technology, Chinese Academy of Sciences (ICT) launched a "big chip" called "Zhejiang". With chiplet design, it includes 16 chiplets with a total of 256 RISC-V cores (each chiplet has 16 RISC-V cores), all of which are programmable and reconfigurable.

The domestic market is potential, and the automotive electronics market is expected to become the next hotspot of RISC-V

MCUs account for approximately 30% of the semiconductor devices used in a car. A traditional car has about 50-100 MCUs, while the number in a smart car will double.

However, the market share of automotive-grade MCUs made in China is less than 5%, which means enormous potential of such MCUs.

In the past, automotive chips were mainly based on ARM or private architectures of some European chip companies. RISC-V offers more options for the research and development of domestic automotive chips. Its open design enables automotive chip vendors to make specific layout according to their own needs, thus enriching product forms.

In recent years, many domestic automotive-grade MCU vendors have chosen RISC-V to build their own MCUs, including Wuhan BinarySemi, NationalChip, LinkedSemi, and ChipEXT.

Among them, NationalChip will explore the application of RISC-V in medium and high-end MCU chips for automotive electronics. For example, CCFC3010PT, for OBC/DC-DC application in new energy power domain, is NationalChip's first automotive-grade MCU chip based on RISC-V. At the same time, the development of CCFC3009PT, which is an MCU chip designed and developed for the autonomous driving field, will start. It mainly targets the post-processing of ISP and radar signals.

CX3288, the automotive-grade MCU launched by ChipEXT in August 2023, adopts a 32-bit RISC-V core. In line with ISO26262 ASIL-B, it supports SHE (Secure Hardware Extension) and Medium HSM in information and cybersecurity, and bolsters communication encryption and secure startup. It also supports AutoSAR, which can provide MCAL and configuration tool support.

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At present, automotive software and tool chains are still fragmented. If an ARM is suitable for all situations, it is difficult to find universality between upper software vendors and operating system and application vendors. Compared with ARM, RISC-V features stronger customization, and its rich extensibility can meet the growing demand of automotive electronic systems in the future. The architecture is free to use, which can reduce the research and development cost and is not restricted by any patent or copyright. Therefore, automotive electronics is expected to become the next hotspot of RISC-V.

Top five automotive chip companies Qualcomm, Bosch, Infineon, NXP, Nordic established Quintauris GmbH in December 2023, focusing on RISC-V. Headquartered in Munich, Germany, the company's CEO is Alexander Kocher (previously served as CEO and president of Elektrobit, an automotive embedded solution provider, and also worked in companies such as Continental, Siemens and Infineon). Initially, the company will pivot on automotive applications, and then gradually expand to mobile devices, Internet of Things chips and other fields.

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However, there are two major challenges in making RISC-V get on vehicles. First, it takes a long time to obtain automotive-grade certification. IATF 16949 should be met, chips should comply with ACQ-100, modules should follow ACQ-104 and ISO26262. Second, it is necessary to establish a sound software ecosystem, including a wider range of operating systems and middleware, and more optimization and verification for specific automotive applications.

Domestic OEMs support RISC-V development and actively cooperate with domestic chip vendors
Some domestic OEMs like Dongfeng Motor, BYD and Chery welcome RISC-V and are keenly cooperating with domestic chip vendors.

In May 2022, Dongfeng Motor took the lead in jointly establishing the "Hubei Province Automotive-grade Chip Industry Technology Innovation Consortium" with CICT, Wuhan Lincontrol Automotive Electronic Systems, Wuhan University of Technology, Huazhong University of Science and Technology, Nuclei System Technology, and TKD Science and Technology.

In December 2022, Wuhan BinarySemi, which was invested by Dongfeng Motor, released Fuxi 2360, a high-performance automotive-grade MCU chip based on RISC-V with the NA900 RISC-V multi-core heterogeneous CPU IP from Nuclei System Technology. It can be used in engines, gearboxes, “electric drive, batteries and electric control", ADAS, vehicle control and other fields.

RISC-V 7_副本.png

In July 2023, Dongfeng Motor announced that the "Hubei Province Automotive-grade Chip Industry Technology Innovation Consortium”, which was led by it, had realized the trial production of three automotive-grade chips which were rare in China and completed the first domestic automotive-grade MCU chip based on RISC-V.

Chery is cooperating with domestic chip vendors to define the entire test architecture of RISC-V, for example, RISC-V-based clients and RISC-V chip testing standards ensure the reliability of RISC-V chips. In addition to chip testing, Chery conducted safety and reliability tests based on automotive-grade regulations, such as AEC-Q100.

BYD collaborates with Huawei to conduct joint research on the chips of Intel or Qualcomm based on RISC-V.

1 How does RISC-V break through?
1.1 Definition and Development History of RISC-V
1.2 Development Milestones of RISC-V
1.3 Classification of Instruction Sets

1.4 Comparison among RISC-V, ARM and X86
1.4.1 Difference between RISC-V and ARM
1.4.2 Comparison between RISC-V and ARM
1.4.3 Business Model Comparison among RISC-V, ARM and X86

1.5 Main Application Scenarios of RISC-V
1.5.1 Automotive Electronics Is Expected to Become the Next Hotspot of RISC-V
1.5.2 Advantages and Disadvantages of RISC-V Processors in Automotive Applications
1.5.3 Application Opportunities of RISC-V in Automotive MCU Operating Systems
1.5.4 Application Opportunities of RISC-V in Cockpit SoC Operating Systems
1.5.5 Application Cases of RISC-V in Cockpit SoC Operating Systems
1.5.6 Application Opportunities of RISC-V in Intelligent Driving SoC Operating Systems
1.5.7 Application Cases of RISC-V in Automotive Chips (1)
1.5.7 Application Cases of RISC-V in Automotive Chips (2)
1.5.7 Application Cases of RISC-V in Automotive Chips (3)
1.5.7 Application Cases of RISC-V in Automotive Chips (4)

1.6 Challenges for RISC-V Getting on Vehicles (1)
1.6.1 Cases of RISC-V Vendors Obtaining Automotive Functional Safety Certification
1.6 Challenges for RISC-V Getting on Vehicles (2)
1.6 Challenges for RISC-V Getting on Vehicles (3)
1.6 Challenges for RISC-V Getting on Vehicles (4)

1.7 How to Promote the Industrialization of RISC-V?
1.7.1 Governments of Countries Have Introduced Policies to Support the Development and Commercialization of RISC-V - Foreign Governments
1.7.2 Governments of Countries Have Introduced Policies to Support the Development and Commercialization of RISC-V - Chinese Government
1.7.3 Five Business Models of RISC-V
1.7.3.1 Model 1
1.7.3.2 Model 2
1.7.3.2.1 Case 1
1.7.3.2.2 Case 2
1.7.3.2.3 Case 3
1.7.3.3 Model 3
1.7.3.4 Model 4
1.7.3.5 Model 5

1.8 How to lower the Threshold of Open Source Chip Development?
1.8.1 Build an Open Source Chip Ecosystem and Reduce Chip Design Cost
1.8.2 Three-step Planning for Building an Independent Open Source Chip Ecosystem
1.8.3 Exploration on Open Source Chip Development Models and Processes
1.8.3.1 Exploration on Open Source Chip Development Processes - Object-oriented Chip Design Methods
1.8.3.2 Exploration on Open Source Chip Development Processes - Establishment of an Agile Verification Platform
1.8.3.3 Exploration on Open Source Chip Development Processes - Exploration on the Verification Based on Open Source Crowdsourcing
1.8.3.4 Exploration on Open Source Chip Development Processes - Open Source EDA Tool Chains
1.8.4 Industry Landscape under Open Source Standards: Three Major Types of RISC-V Players

2 RISC-V Automotive-grade Products and Market Trends
2.1 Trends of RISC-V Market Shipments
2.1.1 Product Summary of Main Automotive RISC-V CPU IP and Chip Vendors (1)
2.1.1 Product Summary of Main Automotive RISC-V CPU IP and Chip Vendors (2)

2.2 Trend 1
2.3 Trend 2

2.4 Trend 3
2.4.1 Case 1
2.4.2 Case 2
2.4.3 Case 3
2.4.4 Case 4
2.4.5 Case 5
2.4.6 Expectations of the Global Industry for Key Nodes of High-performance RISC-V Chips

2.5 Trend 4
2.6 Trend 5

2.7 Trend 6
2.7.1 Case 1
2.7.2 Case 2
2.7.3 Case 3

2.8 Trend 7
2.8.1 Case 1
2.8.2 Case 2

2.9 Trend Discussion: Will RISC-V Replace X86 and ARM?
2.9.1 Development Directions of Global CPU Instruction Sets

2.10 Trend Discussion: The Emerging RISC-V Will Be a Breakthrough for Domestic Automotive Chip Vendors?
2.10.1 Status Quo and Trends of Automotive-grade MCUs: Diversification of Core Architectures in the Automotive MCU Market
2.10.2 Development Opportunities of RISC-V Automotive Chips in the Chinese Market
2.10.3 Many Domestic MCU Vendors Choose RISC-V to Build Automotive-grade MCUs
2.10.4 Cooperation Dynamics in China’s Chip Industry

3 Automotive RISC-V CPU IP and Chip Vendors
3.1 Nuclei System Technology
3.1.1 Profile
3.1 RISC-V CPU IP Product Matrix
3.1.3 NA Automotive-grade Series Certified by ISO 26262 ASIL-D
3.1.4 NA Automotive-grade Series Provides ASIL B and ASIL D Solutions
3.1.5 NA900 & NA300 and Their Security Mechanism Comparison
3.1.6 NA Automotive-grade Series Supports Dual-core Step Locking Mode
3.1.7 Customer Cases of NA Automotive-grade Series
3.1.8 Future Planning of NA Automotive-grade Series
3.1.9 RISC-V Software Development Platform
3.1.10 Cooperation with IAR

3.2 Andes Technology
3.2.1 Profile
3.2.2 Core RISC-V CPU Product Matrix
3.2.3 Development History of RISC-V CPU IP Automotive Functional Safety
3.2.4 AndesCore ISO 26262 Product Roadmap
3.2.5 Main Features of Automotive RISC-V CPU AndesCore? D25F-SE
3.2.6 Main Features of Automotive RISC-V CPU AndesCore? D45-SE
3.2.7 Core Customer Cases of Automotive RISC-V CPU
3.2.8 Automotive Ecosystem
3.2.9 Dynamics in Automotive Ecological Cooperation

3.3 ESWIN
3.3.1 Profile
3.3.2 Product Matrix Based on RISC-V
3.3 RISC-V CPU IP Lineup
3.3.4 Automotive Business Layout
3.3.5 Roadmap of Self-developed RISC-V Processors for Automotive Scenarios
3.3.6 E302A of 32-bit RISC-V Automotive-grade CPU IP Products
3.3.7 E320A of 32-bit RISC-V Automotive-grade CPU IP Products
3.3.8 E330A of 32-bit RISC-V Automotive-grade CPU IP Products
3.3.9 S500A of 32-bit RISC-V Automotive-grade CPU IP Products
3.3.10 Self-developed Domestic RISC-V MCUs
3.3.11 Functional Security Architecture of Self-developed Domestic RISC-V MCUs
3.3.12 Fault Activity and Safety Analysis of Self-developed Domestic RISC-V MCUs
3.3.13 Complete Software Stack of Automotive-grade MCUs Based on RISC-V Processors

3.4 SiFive
3.4.1 Profile
3.4.2 RISC-V-based Processor Core Matrix
3.4.3 Roadmap of Automotive RISC-V Core IP
3.4.4 Main Features of P870-A Automotive Processor Core
3.4.5 Architecture Features of P870-A Automotive Processor Core
3.4.6 Automotive Ecosystem
3.4.7 Cooperation Dynamics in the Automotive Field

3.5 Codasip
3.5.1 Profile
3.5.2 RISC-V Benchmark Processor Matrix
3.5 Architecture of RISC-V CPU L31
3.5.4 Codasip Studio RISC-V EDA tool
3.5.5 Business Model - IP Customized Solutions

3.6 RAMBUS
3.6.1 Hardware Security Cores Based on RISC-V Design
3.6.2 RT-645 Safety Coprocessor for Automotive Applications
3.6.3 Trust Root RT-640 Embedded Hardware Security Module (HSM)

3.7 Renesas
3.7.1 Roadmap of Next-generation MCUs and SoC Solutions: Chiplet Technology Will Be Supported
3.7.2 The Fourth-generation Automotive MCU RH850/U2B Adopts RISC-V as the Core
3.7.3 Internal Framework of RH850/U2B Automotive MCUs

3.8 Tenstorrent
3.8.1 Profile
3.8.2 Chip Roadmap
3.8.3 RISC-V Processor Matrix
3.8.4 Business Model
3.8.5 Cases of Cooperation in Developing Special Chips for Automobiles

3.9 Kneron
3.9.1 Introduction of Automotive AI Edge Chips Based on RISC-V (1)
3.9.2 Introduction of Automotive AI Edge Chips Based on RISC-V (2)
3.9.3 Introduction of Automotive AI Edge Chips Based on RISC-V (3)

3.10 ChipEXT
3.10.1 Profile
3.10.2 MCU Solutions
3.10.3 Launch of Automotive MCUs Based on RISC-V

3.11 WingSemi Technology
3.11.1 Profile
3.11.2 Roadmap of Automotive-grade RISC- IP Products
3.11.3 Main Features of Wing-M500
3.11.4 Business Model
3.11.5 Self-developed WingStudio Agile Development Platform Lowers the Design Threshold of Special Processors

3.12 Mobileye
3.12.1 Development Roadmap of EyeQ Series Chips
3.12.2 Architecture of EyeQUltra Based on RISC-V
3.12.3 Release of EyeQUltra Based on RISC-V

3.13 BinarySemi
3.13.1 Profile
3.13.2 Planning of Automotive-grade MCU Chips and RISC-V Chips
3.13.3 Automotive-grade Fuxi 2360 MCU Chip based on RISC-V (1)
3.13.4 Automotive-grade Fuxi 2360 MCU Chip based on RISC-V (2)
3.13.5 Automotive Chip Ecological Application Construction

3.14 TIH Microelectronics
3.14.1 Profile
3.14.2 Architecture of Automotive-grade T690 Safety MPU Chip
3.14.3 SDK of Automotive-grade T690 Safety MPU Chip
3.14.4 HSM and Network Subsystem of Automotive-grade T690 Safety MPU Chip

3.15 Telink
3.15.1 Profile
3.15.2 Product Lineup
3.15.3 Architecture of Automotive-grade TLSR9 Wireless MCU Based on RISC-V
3.15.4 A Complete Self-developed Protocol Stack for Speeding up Product Launch

3.16 HPMicro
3.16.1 Profile
3.16.2 Main Features of HPM6000 Series RISC-V MCUs
3.16.3 Industrial and Automotive-grade MCU Roadmap
3.16.4 Architecture of Automotive-grade HPM64A0 MCU Based on RISC-V
3.16.5 Application Cases of Automotive-grade HPM64A0 MCU Based on RISC-V
3.16.6 A Complete Ecosystem for Developers

3.17 LinkedSemi
3.17.1 Introduction and Wireless MCU Layout
3.17.2 Automotive-grade Wireless MCUs Based on RISC-V

3.18 NSITEXE
3.18.1 RISC-V Data Stream Processor IP
3.18 RISC-V CPU

4 RISC-V Eco-software Vendors (Automotive Field)
4.1 IAR
4.1.1 Profile
4.1.2 Main Features of IAR Embedded Workbench for RISC-V
4.1.3 Iteration of IAR Embedded Workbench for RISC-V
4.1.4 Functional Safety Certification of IAR Embedded Workbench for RISC-V
4.1.5 RISC-V Functional Safety Application Cases (Automotive Field)

4.2 Arraymo
4.2.1 Profile
4.2 Core Products
4.2.3 RISC-based Operating System Development

4.3 Green Hills Software
4.3.1 μ-veloSity RTOS Supports RISC-V
4.3.2 Cooperation Dynamics in RISC-V

4.4 Vector and Andes Jointly Promote RISC-V AUTOSAR Software Innovation in the Automotive Industry

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